1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to capacitive decoupling systems for integrated circuits and to methods of making the same.
2. Description of the Related Art
Cascode style circuits, such as those frequently used in microprocessors, graphics processors and application specific integrated circuits, typically require full-voltage and midpoint-voltage power supply rails. The on-die decoupling capacitance used to suppress power supply noise is typically also formed by stacking capacitors from a ground rail to the mid-voltage rail and from the mid-voltage rail to the full-voltage rail. This stacking introduces an AC voltage divider which inherently couples noise from the full-voltage rail on to the mid-voltage rail.
The issue of noise from the full-voltage rail coupling over to the mid-voltage rail may be particularly problematic for switching input/output circuits where the noise on the full-voltage rail can be significantly higher than the noise on mid-voltage rail. The reason is that high current draw devices, such as the output stages of input/output drivers or active terminations at the input stages of receivers are connected to the full-voltage rail, while lower power circuits are connected to the mid-voltage rail. One particular example of a high current draw device is an input/output driver for an external random access memory device. Another drawback of the conventional cascode architecture is the filtering nature of the conventional capacitor stack. The conventional capacitor stack serves essentially as an all-pass filter when capacitor leakage effects are considered.
One conventional technique for improving decoupling involves providing more raw capacitance on the die. However, this technique may be severely constrained by the requirements of packing density or will lead to die size growth.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.